The present invention relates to VLSI semiconductor circuits, more particularly to propagating signals on transmission lines in programmable or configurable logic arrays.
User programmable logic arrays and other programmable logic devices may comprise logic elements interspersed in an array of transmission lines. To program a device, the logic elements are configured and the transmission lines are connected together in a pattern to connect the logic elements to each other as desired. In the semiconductor chip, the transmission lines are usually formed as metal segments above a semiconductive substrate in which the logic elements are formed. In order to programmably connect one logic element to another logic element for performing a complex logic function, a transistor having its current carrying terminals permanently connected to two different transmission lines is turned on by programming a device such as a memory cell to supply the control terminal of the transistor with the proper voltage. A transmission line can also be connected to the control terminal of the transistor for controlling the connection between two other transmission lines.
Since a signal in a user programmable logic device may pass through several pass transistors or transmission gates, each of which attenuates the signal, it is periodically necessary to buffer the signal as it is passed from one transmission line to another or as it is passed on a long transmission line. Since the transmission lines are programmably connected after manufacture, it is not possible to know before manufacture the direction of the signal flow between the lines to be connected. In these situations a bidirectional buffer is provided. Copending application Ser. No. 07/013,314 describes such a bidirectional buffer and is incorporated herein by reference.
FIG. 1 shows a logic array in which bidirectional buffers (amplifiers) may be desired. FIG. 1 is an example of a 3-element by 3-element configurable logic array with 12 input/output pads and three different types of logic elements. FIG. 2 shows the legend of interconnect symbols used in FIG. 1. For example node S6-11 of FIG. 1 employs a simple programmable interconnect in which the vertical and horizontal lines may either be connected or not connected. The interconnect at node S10-11 is a full interconnect in which the vertical line may be connected or broken, and in which either of the vertical line segments adjoining node S10-11 may be connected to either of the horizontal line segments adjoining node S10-11. Node B10 employs a bidirectional amplifier or buffer which may be programmably controlled to amplify in either direction.
FIG. 3 shows a circuit diagram of a full interconnect (see legend, FIG. 2) such as S10-11 shown in FIG. 1. It can be seen from FIG. 3 that pass transistors 1 through 6 can be programmed to interconnect any combination of four bidirectional transmission lines 90-1 through 90-4 as desired. FIG. 4 shows a representation of a full interchange in which any of eight bidirectional transmission lines can be programmably connected to any other of the eight bidirectional transmission lines. In FIG. 4, interconnect lines are shown with circled numbers at their ends corresponding to the transmission lines they connect. The pass transistors are not shown in order to simplify the drawing. A complete description of the interchange of FIG. 4 is provided in application Ser. No. 07/013,314.
In FIG. 1, bidirectional amplifiers such as B10 and B24 are shown in each of the horizontal transmission lines. These bidirectional amplifiers are used on transmission lines to prevent the signal from being degraded by too many pass devices. For example, if a signal on output port OUT of logic element 40-1 is to be provided as input to input port IN1 of logic element 40-9, it may be routed through interconnects S6-11, S10-11, S10-20, S18-20 and S18-24. Each interconnect, which takes the signal through the pass transistor, adds resistance and some capacitance to the signal. In order to improve the quality of the signal, buffers such as B10 are provided to amplify and sharpen the signal.
There is a limit to how frequently buffers should be provided. Buffers cost chip space, and when used, add the propagation delay of the buffer to the total propagation time of a signal. Thus in designing a circuit, a comparison is made between the RC delay experienced by a signal when no buffer is used, and the propagation delay experienced by a signal passing through a buffer. These factors are a function of the impedance of a pass transistor channel and the capacitance of the transistor gate of the buffer and of the transmission line. In one preferred design, the ideal number of pass transistors through which a signal propagates between buffers is three to four.
FIG. 5 and FIG. 6 show two bidirectional buffers taught in copending application Ser. No. 07/013,314 and which can be used in FIG. 1 for amplifying the signal on the transmission line at locations such as B10 and B24. These buffers are connected between transmission lines A and B as controlled by pass transistors P1-P4 of FIG. 5 or Q1-Q8 of FIG. 6.
In both FIGS. 5 and 6, the bidirectional buffer is under control of a single memory cell 63. One memory cell can have only two states, "0" or "1". The single memory cell 63 of FIG. 5 controls four pass transistors. The Q output controls N-channel enhancement mode transistors P1 and P2 while the Q output controls N-channel enhancement mode transistors P3 and P4. When memory cell 63 holds a logic "1" at node Q, transistors P1 and P2 are ON, output terminal 62 of bidirectional buffer 64 is connected to transmission line A and input terminal 61 is connected to transmission line B. Transistors P3 and P4 are OFF, thus the buffer is connected to amplify a signal as it is propagated from line B to line A. The opposite state of memory cell 63 connects the buffer to amplify in the opposite direction.
The bidirectional buffer of FIG. 6 works in a similar manner, with transistor pairs such as Q1 and Q2 replacing single transistors such as P1. In FIG. 6, transistor Q1 is an N-channel transistor and transistor Q2 is a P-channel transistor. A high signal from the Q output terminal of memory cell 63 turns on transistor Q1 at the same time as a low signal from the Q output terminal of memory cell 63 turns on transistor Q2. Likewise, each of the other pairs of transistors is connected so that the transistors in the pair operate together. Operation of these buffers is explained more fully in copending application Ser. No. 07/013,314.
As controlled by single memory cell 63, the buffers of FIG. 5 and FIG. 6 do not have a high impedance state, that is, a state in which lines A and B are not connected. This condition of being always ON can create a problem during configuration of a logic array such as that of FIG. 1. Configuration consists of loading the appropriate data into the memory cells controlling the pass transistors and buffers of the configurable logic array. A voltage is usually present on some of the transmission lines during configuration of the programmable elements and interconnects because the same power supply which provides power for programming is preferably used to provide power to the logic array during operation. During programming, it is not always possible to prevent buffer output leads from being temporarily connected to each other.
Memory cells can be initially set or reset such that all bidirectional buffers point in the same direction, for example in FIG. 1, setting the output leads of all buffers such as B10 and B24 in horizontal lines to point to the right. This will reduce but not eliminate the chance of buffer output leads being temporarily connected to each other during the configuration process.
Connecting one buffer output to another will occur when some buffers have been set to the final direction and other buffers have not yet been set. The simplest order of programming the controls is not related to the values to be programmed on the controls. Layout of the memory cells controlling the various pass transistors and buffers locates the buffers and memory cells in a somewhat random order with respect to each other. Cells for controlling buffers are intermixed with cells for controlling pass transistors. It is not convenient to program all buffers before programming any pass transistors.
Consider the following example in which buffer output terminals are temporarily connected together.
Let us assume that the bidirectional buffers including buffers B10 and B24 of FIG. 1 have been initially set so that their output directions point right, and that a user wishes to connect output lead OUT of element 40-1 to input leads IN1 of both elements 40-8 and 40-9. The selected route will be through interconnects S6-11, S10-11, S10-20, S18-20, and both S18-16 and S18-24. Among other interconnects to be programmed in the logic array, the memory cell controlling interconnect S6-11 will be set so that S6-11 is ON. Interconnect S10-11 will be configured so that line Y11a is connected to line X10b. Buffer B10 connects line X10b and line X10c together and it remains directed so that its output port points to the right and its input port points to the left. Interconnect S10-20 will be configured so that line X10c is connected to line Y20b. Interconnect S18-16 will be configured so that input port IN1 of logic element 40-8 is connected to line X18b. Buffer B24 will be redirected so that its output port points to the left, and its input port points to the right. Interconnect S18-20 will be configured so that both line X18c and line X18d are connected to line Y20b. And interconnect S18-24 is configured so that line X18d is connected to input port IN1 of element 40-9.
Let us assume that because of the layout of the components interconnects S10-20 and S18-20 are programmed before buffer B24 is reoriented. In this interim period, the outputs of buffers B10 and B24 are connected together through lines X10c, Y20b, and X18c. In this interim period if a high signal is applied to the input lead of buffer B10 and a low signal is applied to the input lead of buffer B24, there will be a short circuit from the supply voltage to ground through the two buffers. Such a high current situation can cause drooping of the power supply voltage with a resultant improper programming of subsequent memory cells. It is also possible that such a high current could damage or destroy the chip during programming.
Many other examples can be imagined in which additional care must be taken to avoid creating such shorts.
One way to avoid such shorts with the current buffers is to program the directions of all buffers before turning on any pass transistors to interconnect elements of the array. However, it is not efficient to program all memory cells for bidirectional buffers before turning on any pass transistors. To orient all buffers before turning on any pass transistors requires extra circuitry to program in a random access fashion rather than moving sequentially from one side of the chip to the other, which in turn requires larger chip size. It is preferable to use a simpler algorithm.